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9288i-auto-09/14 features fully iso 11898-2,-5, sae j2284 compliant can fd ready communication speed up to 5mbit/s low electromagnetic emission (eme) an d high electromagnetic immunity (emi) differential receiver with wide common mode range atmel ata6560: silent mode (receive only) remote wake-up capability via can bus functional behavior predictable under all supply conditions transceiver disengages from the bus when not powered up rxd recessive clamping detection high electrostatic discharge (esd) handling capability on the bus pins bus pins protected against transients in automotive environments transmit data (txd) dominant time-out function undervoltage detection on vcc and vio pins canh/canl short-circuit and overtemperature protected qualified according to aec-q100 packages: so8, dfn8 with wettable flanks (moisture sensitivity level 1) description the atmel ? ata6560/ata6561 is a high-speed can tr ansceiver that provides an interface between a controller area network (can) protocol controller and the physical two-wire can bus. the transceiver is designed for high-spe ed (up to 5mbit/s) can applications in the automotive industry, providing di fferential transmit and receive capability to (a microcon- troller with) a can protocol controller. it of fers improved electromagnetic compatibility (emc) and electrostatic discharge (esd) perfo rmance, as well as features such as: ideal passive behavior to the can bus when the supply voltage is off direct interfacing to microcontrollers with supply voltages from 3v to 5v (ata6561) ata6560/ata6561 high-speed can transcei ver with standby mode can fd ready datasheet
ata6560/ata6561 [datasheet] 9288i?auto?09/14 2 three operating modes together with the dedicated fail-saf e features make the atmel ata6560/ata6561 an excellent choice for all types of high- speed can networks, especially in nodes requiring low-power mode with wake-up capability via the can bus. figure 1. block diagram notes: 1. pin 5: atmel ata6561: vio atmel ata6560: nsil (the vio line and the vcc line are internally connected) 2. hsc: high-speed comparator 3. wuc: wake-up comparator temperature protection control unit wake-up filter slope control and driver txd time-out- timer vio vio (1) vio (1) vio (1) vcc v cc mux 1 2 txd stby canh ata6560/ata6561 rxd nsil 8 7 5 (1) 3 4 canl gnd 6 5 (1) vio (1) wuc (3) hsc (2)
3 ata6560/ata656 1 [datasheet] 9288i?auto?09/14 1. pin configuration figure 1-1. so8 pinning figure 1-2. dfn8 pinning table 1-1. pin description pin symbol function 1 txd transmit data input 2 gnd ground supply 3 vcc supply voltage 4 rxd receive data output; reads out data from the bus lines 5 (1) vio supply voltage for i/o level adapter; only in the atmel ata6561 5 (1) nsil silent mode control input (low ac tive); only in the atmel ata6560 6 canl low-level can bus line 7 canh high-level can bus line 8 stby standby mode control input backside (2) - heat slug, internally connected to the gnd pin notes: 1. the function of pin 5 depends on the version: atmel ata6561: vio; atmel ata6 560: nsil (the vio line and the v cc line are internally connected) 2. only for the dfn8 package 1 2 3 4 8 5 txd gnd vcc ata6561 rxd stby canh canl vio 7 6 1 2 3 4 8 5 txd gnd vcc ata6560 rxd stby canh canl nsil 7 6 stby canl canh vio txd vcc gnd rxd ata6561 stby canl canh nsil txd vcc gnd rxd ata6560
ata6560/ata6561 [datasheet] 9288i?auto?09/14 4 2. functional description the atmel ? ata6560/ata6561 is a stand-alone high-speed ca n transceiver compliant with the iso 11898-2 and 11898-5 can standard. it provides a very low current consum ption in standby mode and wake-up capability via the can bus. there are two versions available, on ly differing in the function of pin 5: atmel ata6561: the pin 5 is the vio pin and should be connect ed to the microcontroller su pply voltage. this allows direct interfacing to microcontrollers with supply voltages do wn to 3v and adjusts the signal levels of the txd, rxd, and stby pins to the i/o levels of the microcontr oller. the i/o ports are supplied by the vio pin. atmel ata6560: the pin 5 is the control input for silent mode nsil allowing the ata6560 to only receive data but not send data via the bus. the output driver stage is disabl ed. the vio line and the vcc line are internally connected, this sets the signal levels of the txd, rxd, stby, and ns il pins to levels compatible with 5v microcontrollers. 2.1 operating modes the atmel ata6561 supports three operating modes: unpowered, standby and normal. the atmel ata6560 additionally has the silent mode. these modes can be selected via the stby and nsil pins. see figure 2-1 and table 2-1 for a description of the operating modes. figure 2-1. operating modes note: for the atmel ata6561 nsil is internally set to ?1?. table 2-1. operating modes mode inputs outputs stby nsil pin txd can driver pin rxd unpowered x (3) x (3) x (3) recessive recessive standby high x (3) x (3) recessive active (4) silent (ata6560) low low x (3) recessive active (1) normal low high (2) low dominant low low high (2) high recessive high notes: 1. low if the can bus is dominant, high if the can bus is recessive. 2. internally pulled up if not bonded out. 3. irrelevant 4. reflects the bus only for wake-up vcc < v uvd(vcc) vcc < v uvd(vcc) stby = 1 stby = 1 stby = 0 and nsil = 1 and stby = 0 and (nsil = 0 or txd = 0) stby = 0 and txd = 0 nsil = 1 and txd = 1 and error = 0 nsil = 0 or error = 1 txd = 1 and error = 0 vcc > v uvd(vcc) vcc < v uvd(vcc) unpowered mode standby mode silent mode normal mode vcc < v uvd(vcc) or stby = 1 stby = 0 and txd = 1 and error = 0 and txd = 1 * * silent mode is externally not accessible error = 1 error = 0 vcc < v uvd(vcc) or vio < v uvd(vio) vio < v uvd(vio) vcc < v uvd(vcc) or vcc > v uvd(vcc) and vio < v uvd(vio) vio > v uvd(vio) unpowered mode standby mode silent mode normal mode ata6560 ata6561 stby = 1
5 ata6560/ata656 1 [datasheet] 9288i?auto?09/14 2.1.1 normal mode a low level on the stby pin together with a high level on pi ns txd and nsil selects the normal mode. in this mode the transceiver is able to transmit and receive data via the canh and canl bus lines (see figure 1 on page 2 ). the output driver stage is active and drives data from the txd input to the can bus. the high-speed co mparator (hsc) converts the analog data on the bus lines into digital data which is out put to pin rxd. the bus biasing is set to vcc/2 and the undervoltage monitoring of vcc is active. the slope of the output signals on the bus lines is controlled and optimized in a way that guarantees the lowest possible electromagnetic emission (eme). to switch the device in normal operating mode, set the stby pi n to low and the txd pin and the nsil pin (if applicable) to high (see table 2-1 on page 4 , figure 2-2 and figure 2-3 ). the stby and the nsil pins each provide a pull-up resistor to vio, thus ensuring defined levels if the pins are open. please note that the device cannot enter normal m ode as long as txd is at ground level. atmel ? ata6560 will only switch to normal mode when all inputs are set accordingly. the switching into normal mode is depicted in the following two figures. figure 2-2. switching from standby mode to normal mode (nsil = high) figure 2-3. switching from silent mode to normal mode stby txd standby mode t del(stby-norm) = 47s max normal mode t t t operation mode stby nsil txd silent mode t del(sil-norm) = 10s max normal mode t t t t operation mode
ata6560/ata6561 [datasheet] 9288i?auto?09/14 6 2.1.2 silent mode (only with the atmel ata6560) a low level on the nsil pin (available on pin 5) and on the stby pin selects silent mode. this receive-only mode can be used to test the connection of the bus medium. in silent mode the atmel ata6560 can still rece ive data from the bus, but the transmitter is disabled and therefore no data can be sent to the can bus. the bus pins are re leased to recessive state. all other ic functions, including the high-speed comparator (hsc), continue to operate as they do in normal mode. silent mode can be used to prevent a faulty can controlle r from disrupting all network communications. 2.1.3 standby mode a high level on the stby pin selects standby mode. in this mode th e transceiver is not able to transmit or correctly receive data via the bus lines. the transmitter and the high-speed compar ator (hsc) are switched off to reduce current consumption and only the low- power wake-up comparator (wuc) monitors the bus lines for a valid wake-up signal. a signal change on the bus from ?recessive? to ?dominant? followed by a dominant state longer than t wake switches the rxd pin to low to signal a wake-up request to the microcontroller. in standby mode the bus lines are biased to ground to reduce current consumption to a minimum. the wake-up comparator (wuc) monitors the bus lines for a valid wake-up signal. when the rxd pin switches to low to signal a wake-up request, a transition to normal mode is not triggered until the stby pin is forced back to low by the microcontroller. a bus dominant time-out timer prevents the device fr om generating a permanent wake-up request by switching the rxd pin to high. for atmel ? ata6560 only: in the event the nsil input pin is set to low in standby mode, the internal pull-up resistor causes an additional quiescent current from vio to gnd. atmel therefore recommends setting the nsil pin to high in standby mode. 2.2 fail-safe features 2.2.1 txd dominant time-out function a txd dominant time-out timer is started when the txd pin is set to low. if the low state on the txd pin persists for longer than t to(dom)txd , the transmitter is disabled, releasing the bus lines to recessive state. this function prevents a hardware and/or software application failure from driving the bus lines to a perma nent dominant state (blocking all network communications). the txd dominant time-out timer is reset when the txd pin is set to high ( 4s). 2.2.2 internal pull-up structure at the txd, nsil, and stby input pins the txd, stby, and nsil pins have an intern al pull-up to vio. this ensures a safe, de fined state in case one or all of these pins are left floating. pull-up currents flow in these pins in all states, meaning all pins should be in high state during stan dby mode to minimize the current consumption. 2.2.3 undervoltage detection on pins vcc and vio if v vcc or v vio drop below their respective undervoltage detection levels (v uvd(vcc) and v uvd(vio) (see section 6. ?electrical characteristics? on page 9 ), the transceiver switches off and disengages from the bus until v vcc and v vio have recovered. the low-power wake-up comparator is only switched off during a v cc or vio undervoltage. the logic state of the stby pin is ignored until the vcc voltage or the vio voltage has recovered. 2.2.4 bus wake-up time-out function in standby mode a bus wake-up time-out timer is started when the can bus changes from recessive to dominant state. if the dominant state on the bus persists for longer than t to_bus , the rxd pin is switched to high. this function prevents a clamped dominant bus (due to a bus short-circuit or a failure in one of the other nodes on the networ k) from generating a permanent wake-up request. the bus wake-up time-out timer is reset w hen the can bus changes from dominant to recessive state. 2.2.5 overtemperature protection the output drivers are protec ted against overtemperat ure conditions. if the junction temperature exceeds the shutdown junction temperature, t jsd , the output drivers are disabled until the junction temperature drops below t jsd and pin txd is at high level again. the txd condition ensures that output dr iver oscillations due to temperature drift are avoided.
7 ata6560/ata656 1 [datasheet] 9288i?auto?09/14 figure 2-4. release of transmission after overtemperature condition 2.2.6 short-circuit protection of the bus pins the canh and canl bus outputs are short- circuit protected, either against gnd or a positive supply voltage. a current- limiting circuit protects the transceiver against damage. if the device is heating up due to a continuous short on canh or canl, the internal overtemperature protec tion switches the bus transmitter off. 2.2.7 rxd recessive clamping this fail-safe feature prevents the controller from sending da ta on the bus if it?s rxd line is clamped to high (e.g., recessive). that is, if the rxd pin cannot signalize a dominant bus condition because it is e.g, shorted to vcc, the transmitter within ata6560/ata 6561 is disabled to avoid possible data collisi ons on the bus. in normal and silent mode (only ata6560), the device permanently com pares the state of the high-speed compar ator (hsc) with the state of the rxd pin. if the hsc indicates a dominant bus state for more than t rc_det without the rxd pin doing the same, a recessive clamping situation is detected and the device is forced into s ilent mode. this fail-safe mode is released by either entering standby or unpowered mode or if the rxd pin is showing a dominant (e.g., low) level again. figure 2-5. rxd recessi ve clamping detection failure overtemp gnd txd overtemperature rdr t t t ot bus v diff (canh-canl) v io rd d t t rxd v io gnd can txd rxd operation mode normal normal silent if the clamping condition is removed and a dominant bus is detected, the transceiver goes back to normal mode.
ata6560/ata6561 [datasheet] 9288i?auto?09/14 8 3. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters condition symbol min. max. unit canh, canl dc voltage transient voltage, according to iso 7637 part 2 v canh , v canl ?27 ?150 +42 +100 v v dc voltage on all other pins v x ?0.3 +5,5 v esd according to ibee lin emc test spec. 1.0 following iec 61000-4-2 - pin canh, canl 8 kv esd (hbm followin g stm5.1 with 1.5k /100pf) - pin canh, canl to gnd 6 kv component level esd (hbm acc. ansi/esd stm5.1) jesd22-a114 aec-q100 (002) 4 kv cdm esd stm 5.3.1 750 v esd machine model aec-q100-revf(003) 200 v operating range for junction temperature t j ?40 +150 c storage temperature t stg ?55 +150 c 4. thermal characteristics so8 parameters symbol min. typ. max. unit thermal resistance junction to ambient r thja 145 k/w thermal shutdown of the bus drivers t jsd 150 175 195 c 5. thermal characteristics dfn8 parameters symbol min. typ. max. unit thermal resistance junction to heat slug r thjc 10 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb according to jedec r thja 50 k/w thermal shutdown of the bus drivers t jsd 150 175 195 c
9 ata6560/ata656 1 [datasheet] 9288i?auto?09/14 6. electrical characteristics t j = ?40c to +150c; v cc = 4.5v to 5.5v; v io = 2.8v to 5.5v; r l = 60 , c l = 100pf unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the ic. no. parameters test conditions symbol min. typ. max. unit type* 1 supply, pin v cc 1.1 supply voltage v cc 4.5 5.5 v a 1.2 supply current in silent mode silent mode, v txd = v vio i vcc_sil 1.9 2.5 3.0 ma a 1.3 supply current in normal mode - recessive, v txd = v vio - dominant, v txd = 0v i vcc_rec i vcc_dom 2 20 50 5 70 ma ma a 1.4 supply current in stby mode vcc = vio, v txd = v nsil = v io ta = 2 5 c i vcc_stby i vcc_stby 7 12 a a a d 1.5 undervoltage detection threshold on pin vcc v uvd(vcc) 2.75 4.5 v a 2. i/o level adapter supply, pin vio (1) (only with the atmel ata6561) 2.1 supply voltage on pin vio v vio 2.8 5.5 v a 2.2 supply current on pin vio normal and silent mode - recessive, v txd = v vio - dominant, v txd = 0v stby mode i io_rec i io_rdom i io_stby 10 50 80 350 250 500 1 a a a a a a 2.3 undervoltage detection threshold on pin vio v uvd(vio) 1.3 2.7 v a 3 mode control input, pin nsil and stby 3.1 high-level input voltage v ih 0.7 v vio v vio + 0.3 v a 3.2 low-level input voltage v il ?0.3 0.3 v vio v a 3.3 pull- up resistor to vio v stby = 0v v nsil =0v rpu 75 125 175 k ? a 3.4 high-level leakage current v stby = v vio v nsil = v vio i l ?2 +2 a a 4 can transmit data input, pin txd 4.1 high-level input voltage v ih 0.7 v vio v vio + 0.3 v a 4.2 low-level input voltage v il ?0.3 0.3 v vio v a 4.3 pull-up resistor to vio v txd = 0v r txd 20 35 50 k ? a 4.4 high-level leakage current normal mode, v txd = v vio i txd ?2 +2 a a 4.5 input capacitance c txd 5 10 pf d 5 can receive data output, pin rxd 5.1 high-level output current normal mode, v rxd = v vio ? 0.4v, v vio = v vcc i oh ?8 ?1 ma a 5.2 low-level output current normal mode, v rxd = 0.4v, bus dominant i ol 2 12 ma a 6 bus lines, pins canh and canl 6.1 dominant output voltage v txd = 0v, t < t to(dom)txd - pin canh - pin canl i io 2.75 0.5 3.5 1.5 4.5 2.25 v v a 6.2 transmitter dominant voltage symmetry v dom(tx)sym = v vcc ? v canh ? v canl v dom(tx)sym ?400 +400 mv a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. only for atmel ata6560; otherwise the va lues are part of the vcc pin specification.
ata6560/ata6561 [datasheet] 9288i?auto?09/14 10 6.3 bus differential output voltage v txd = 0v, t < t to(dom)txd r l = 45 to 65 v vcc =4.75v to 5.25v v txd = v vio , receive, no load v o(dif)bus 1.5 ?50 3 +50 v mv a 6.4 recessive output voltage normal and silent modes, v txd =v vio , no load v o(rec) 2 0.5 x v vcc 3 v a 6.5 differential receiver threshold voltage (hsc) normal and silent modes, v cm(can) = ?27v to +27v v th(rx)dif 0.5 0.7 0.9 v a 6.6 differential receiver hysteresis voltage (hsc) normal and silent modes, v cm(can) = ?27v to +27v v hys(rx)dif 50 120 200 mv a 6.7 dominant output current v txd = 0v, t < t to(dom)txd, v vcc = 5v - pin canh, v canh = 0v - pin canl, v canl = 5v/40v i io(dom) ?100 35 ?35 100 ma ma a 6.8 recessive ou tput current normal and silent modes, v txd =v vio , no load, v canh =v canl = ?27v to +32v i io(rec) ?5 +5 ma a 6.9 leakage current v vcc =v vio = 0v, v canh =v canl = 5v i io(rec) ?5 0 +5 a a 6.10 input resistance r i 9 15 28 k ? a 6.11 input resistance deviation between v canh and v canl r i ?1 0 +1 % a 6.12 differential input resistance r i(dif) 19 30 52 k a t j < 125c r i(dif) 20 30 52 k b 6.13 common-mode input capacitance c i(cm) 20 pf d 6.14 differential input capacitance c i(dif) 10 pf d 8 transceiver timing, pins canh, canl, txd, and rxd, see figure 6-1 and figure 6-2 8.1 delay time from txd to bus dominant normal mode t d(txd-busdom) 40 130 ns c 8.2 delay time from txd to bus recessive normal mode t d(txd-busrec) 40 130 ns c 8.3 delay time from bus dominant to rxd normal and silent modes t d(busdom- rxd) 20 100 ns c 8.4 delay time from bus recessive to rxd normal and silent modes t d(busrec-rxd) 20 100 ns c 8.5 propagation delay from txd to rxd normal mode rising edge at pin txd falling edge at pin txd t pd(txd-rxd) 40 40 200 200 ns ns a a normal mode r l = 120 , c l = 200pf rising edge at pin txd falling edge at pin txd t pd(txd-rxd) 300 300 ns ns d d 8.6 txd dominant time-out time v txd = 0v, normal mode t to(dom)txd 0.8 3 ms a 8.7 bus wake-up time-out time standby mode t to_bus 0.8 3 ms a 6. electrical characteristics (continued) t j = ?40c to +150c; v cc = 4.5v to 5.5v; v io = 2.8v to 5.5v; r l = 60 , c l = 100pf unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the ic. no. parameters test conditions symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. only for atmel ata6560; otherwise the va lues are part of the vcc pin specification.
11 ata6560/ata656 1 [datasheet] 9288i?auto?09/14 figure 6-1. timing test circuit for the atmel ata6 560/ata6561 can transceiver 8.8 min. dominant time for bus wake-up standby mode t wake 0.75 3 5 s a 8.9 delay time for standby to normal mode transition falling edge at pin stby nsil = high t del((stby-norm) 47 s a 8.10 delay time for normal mode to standby mode transition rising edge at pin stby nsil = high t del(norm-stby) 5 s d 8.11 delay time for normal mode to silent mode transition falling edge at pin nsil stby = low t del(norm-sil) 10 s d 8.12 delay time for silent mode to normal mode transition rising edge at pin nsil stby = low t del(sil-norm) 10 s d 8.13 delay time for silent mode to standby mode transition rising edge at pin stby nsil = low t del(sil-stby) 5 s d 8.14 delay time for standby mode to silent mode transition falling edge at pin stby nsil = low t del(stby-sil) 47 s d 8.15 debouncing time for recessive clamping state detection v(canh-canl) > 900mv rxd = high t rc_det 90 ns d transceiver timing for higher bit rates, pins canh, canl, txd, and rxd, see figure 6-1 and figure 6-3 on page 12 8.16 recessive bit time on pin rxd normal mode, t bit(txd) = 500ns t bit(rxd) 400 550 ns d normal mode, t bit(txd) = 200ns t bit(rxd) 120 220 ns a 6. electrical characteristics (continued) t j = ?40c to +150c; v cc = 4.5v to 5.5v; v io = 2.8v to 5.5v; r l = 60 , c l = 100pf unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the ic. no. parameters test conditions symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. only for atmel ata6560; otherwise the va lues are part of the vcc pin specification. txd 1 4 7 6 5 28 3 + +5v 22f 100nf 15pf rxd canh gnd stby canl vio/nsil vcc r l c l
ata6560/ata6561 [datasheet] 9288i?auto?09/14 12 figure 6-2. can transcei ver timing diagram figure 6-3. can transceiver timing diagram for loop delay symmetry note: the bit time of a recessi ve bit after five dominant bits is measured on the rxd pin. txd canh high low high recessive low dominant 0.9v 0.5v canl rxd v o(dif) (bus) t d(txd-busdom) t d(txd-busrec) t d(busdom-rxd) t pd(txd-rxd) t pd(txd-rxd) t d(busrec-rxd) 0.7v io 0.3v io 30% 70% 30% 30% 70% 5 x t bit(txd) t bit(txd) t bit(rxd) t loop, falling edge t loop, rising edge txd rxd
13 ata6560/ata656 1 [datasheet] 9288i?auto?09/14 7. application circuits figure 7-1. typical applicat ion circuit atmel ata6561 figure 7-2. typical applicat ion circuit atmel ata6560 note: for dfn8 package: heat slug must always be connected to gnd. 7 8 1 4 5 2 3 canh 100nf 22f (1) vio vcc + vdd microcontroller gnd ata6561 canh stby txd rxd canl bat 5v 12v 6 canl gnd gnd 3.3v 12v (1) the size of this capacitor depends on the used external voltage regulator. 100nf 7 8 5 4 2 3 canh vcc vdd microcontroller gnd ata6560 canh stby nsil 1 txd rxd canl bat 100nf 6 canl gnd 5v 12v (1) the size of this capacitor depends on the used external voltage regulator. gnd 22f (1) +
ata6560/ata6561 [datasheet] 9288i?auto?09/14 14 8. ordering information extended type number package remarks ata6560-gbqw dfn8 can transceiver, pb-free, 6k, taped and reeled ata6560-gaqw so8 can transceiver, pb-free, 4k, taped and reeled ata6561-gbqw dfn8 can transceiver, pb-free, 6k, taped and reeled ata6561-gaqw so8 can transceiver, pb-free, 4k, taped and reeled
15 ata6560/ata656 1 [datasheet] 9288i?auto?09/14 9. package information figure 9-1. so8 package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5185.01-4 1 05/08/14 package: so8 common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.15 0.25 0.1 a1 3.9 4 3.8 e1 0.4 0.5 0.3 b 1.27 bsc e 0.2 0.25 0.15 c 0.65 0.9 0.4 l 66.2 5.8 e 4.9 5 4.8 d 1.47 1.55 1.4 a2 1.65 1.8 1.5 a 85 14 d b e a a1 a2 c e1 e l pin 1 identity
ata6560/ata6561 [datasheet] 9288i?auto?09/14 16 figure 9-2. dfn8 package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5165.03-4 1 10/11/13 package: vdfn_3x3_8l exposed pad 2.4x1.6 common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.035 0.05 0 a1 33.1 2.9 e 0.3 0.35 0.25 b 0.65 e 0.4 0.45 0.35 l 1.6 1.7 1.5 e2 2.4 2.5 2.3 d2 33.1 2.9 d 0.21 0.26 0.16 a3 0.85 0.9 0.8 a d 1 8 pin 1 id partially plated surface e a a3 a1 b l z 10:1 top view side view bottom view e d2 14 85 e2 z
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